A hardware-centric project aiming to design a Scientific Calculator using Verilog (RTL). The calculator will support basic arithmetic operations alongside advanced features like statistical calculations and polynomial equation solving. The design follows a behavioral approach for all computational operations, with a Display module developed in parallel to visualize calculations. An Instruction Set Architecture (ISA) will be integrated into the core CPU to load sprites into the Display Module and handle computation tasks. Upon completing the calculator and display functionalities, the design will be processed through the open-source ASIC implementation tool OpenLane, transforming it into an ASIC-ready chip.